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Short Form Specs

Figure 7. STD 32 compliance product descriptor feature listing

Feature Description Additional Signal Support
A16 SA 16-bit I/0 address decode (I/0 Slave)/ generation (master) A0-A15
A24 SA 24-bit memory address decode (Memory Slave)/generation (master) A0-A24
D8 SA 8-bit data transfer, masters/slaves D0-D7
D16 SA16-bit transfer, masters/slaves D0-D15,MEM16*,BHE*,IO16*
EBURST EA Burst transfer capability, masters/slaves SLBURST*,MSBURST*
EDMAA EA type A DMA transfers supported, masters/slaves DMAIOW*,DMAIOR*, DRQx,DAKx*,T-C
EDMAB EA type B DMA transfers supported, masters/slaves DMAIOW*,DMAIOR*, DRQx, DAKx*,T-C
EDMAC EA type C DMA transfers supported, masters/slaves DMAIOW*,DMAIOR*, DRQx, DAKx*,T-C, SLBURST*, MSBURST*
GAX EA geographical address support masters/slaves AENx* (masters)
I SA (STD-80) interrupt generation (slaves)/ servicing (masters) on INTRQ*, INTR1*,NMIRQ*, CNTRL* (INTRQ2*), or INTRQ3* INTRQ*,INTRQ1*,NMIRQ*[CNTRL* (INTRQ2*)], INTRQ3*
ICA Cascadable interrupt address support, masters/slaves A8-A10 during INTA
IXP Slot-specific interrupt servicing (Permanent Masters)/ generation (slaves), positive edge-triggered IRQx
IXL Slot-specific interrupt servicing (Permanent Masters)/ generation (slaves), low-level asserted IRQx
MB Bus arbitration via BUSRQ*/BUSAK* - SA Masters only BUSRQ*,BUSAK*
MD Bus Arbitration via DREQx*/DAKx* - SA Masters only DREQx*, DAKx*
MX Bus Arbitration via MREQx*/MAKx* (Permanent Master)/ request (Temporary Slave) MREQx*,MAKx*
NOWS No wait-state (NOWS*) support NOWS*
SDMA8 8-bit SA frontplane DMA as specified in Chapter 2, masters/slaves --
SDMA16 16-bit SA frontplane DMA as specified in Chapter 2, masters/slaves --
XA16 EA 16-bit address decode, I/0 transfers A2-A15, BE0*-BE3* as per Chapter 3
XA32 Full 32-bit EA address space driven, masters may pull XA24*-XA31* passively high Full 32-bit EA address decoded by Memory Slaves A2-A15, XA16-XA23, XA24* XA31*, BE0*-BE3*
XD8 8-bit EA data transfer, masters/slaves D0-D7
XD16 16-bit EA data transfer, masters/slaves D0-D15, EX16*, BE0*-BE3*
XD32 32-bit EA data transfer, masters/slaves D0-D31, EX16*, EX32*, EX32* BE0* BE3*
[Return to STD 32 Short-Form Specification Page]


 
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3888 Stewart Road - Eugene, OR 97402

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