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Short Form Specs

Figure 6. STD 32 compliance board MODES

STD 32 BOARD MODE DEFINITION
Permanent Master Bus master that drives CLOCK*, monitors PBRESET*, and drives SYSRESET*
Temporary Master Bus Master that requests the bus via BUSRQ*, MREQx, or DREQx*
I/0 Slave Slave that decodes and responds to SA or EA I/0 cycles
Memory Slave Slave that decodes and responds to SA or EA memory cycles
Arbiter (Mn, Dn) System arbiter that manages n MREQx*/MAKx* signals and/or n DREQx*/DAKx* signals for arbitration
[Return to STD 32 Short-Form Specification Page]


 
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