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Short Form Specs

Figure 3. This table illustrates the STD 32 Bus P Pinouts. See Figure 4 for a description of the E Pinouts.

COMPONENT SIDE   CIRCUIT SIDE
Pin Mnemonic Signal Flow Description   Pin Mnemonic Signal Flow Description
1 +5VDC In Logic Power   2 +5VDC In Logic Power
3 GND In Logic Ground   4 GND In Logic Ground
5 VBAT Bidir Battery Power   6 DCPDN* Bidir DC Power Down
7 A19/D3 Out/Bidr Address/Data   8 A23/D7 Out/Bidr Address/Data
9 A18/D2 Out/Bidr Address/Data   10 A22/D6 Out/Bidr Address/Data
11 A17/D1 Out/Bidr Address/Data   12 A21/D5 Out/Bidr Address/Data
13 A16/DO Out/Bidr Address/Data   14 A20/D4 Out/Bidr Address/Data
15 A7 Out Address   16 A15 Out Address
17 A6 Out Address   18 A14 Out Address
19 A5 Out Address   20 A13 Out Address
21 A4 Out Address   22 A12 Out Address
23 A3 Out Address   24 A11 Out Address
25 A2 Out Address   26 A10 Out Address
27 A1 Out Address   28 A9 Out Address
29 AO Out Address   30 A8 Out Address
31 WR* Out Write Mem or I/0   32 RD* Out Read Mem or I/0
33 IORQ* Out I/0 Address Select   34 MEMRQ* Out Mem Address Select
35 IOEXP Out I/0 Expansion   36 BHE* Out Byte High Enable
37 INTRQ1* In Interrupt Request 1   38 ALE* Out Address Latch Enable
39 STATUS1* Out CPU Status 1   40 STATUS0* Out CPU Status 0
41 BUSAK* Out Bus Acknowledge   42 BUSRQ* In Bus Request
43 INTAK* Out Interrupt
Acknowledge		   44 INTRQ* In Interrupt Request
45 WAITRQ* In Wait Request   46 NMIRQ* In Non-Maskable
Int Request
47 SYSRESET* Out System Request   48 PBRESET* In Push-Button Reset
49 CLOCK* Out Clock   50 CNTRL* Bidir Aux Timing
51 PCO Out Priority Chain Out   52 PCI In Priority Chain In
53 AUX GND In AUX Ground (bussed)   54 AUX GND In AUX Ground (bussed)
55 AUX+V In AUX Positive
(+12VDC)		   56 AUX+V In AUX Positive (+12VDC)
Notes: An asterisk (*) indicates a low level active signal. Address lines A16 to A23 are multiplexed on data lines D0 to D7 on each address cycle for STD-80 compatibility. PCO and PCI are not typically used on peripheral cards. All boards not supporting PCO and PCI should tie these two signals together.

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