Short Form Specs

 Contents
Overview
Mechanical
Electrical
Compliance

The STD 32 Bus Specification: A Brief Overview

The STD 32 Bus Specification extends the capabilities of the STD 80 Series standard, while remaining compatible with existing STD Bus cards. These excerpts from the specification provide mechanical and electrical details pertinent to a technical evaluation of the bus. For more information or the complete specification, contact VersaLogic.

Mechanical

Connectors
The 136-pin STD 32 card connector uses cantilever beam construction with a hemispherical contact point. This connector/contact style is similar to EISA and Micro Channel designs, and is considered one of the most reliable in the industry (see Figure 1).

Connector Specifications

Number of Contacts:

136

Contact Design:

Cantilever beam, hemispherical contact point

Contact Plating:

30 µinches of gold over

50 µinches nickel (minimum)

Current Capacity:

1.0 Amp (minimum per pin)

Mating PCB Thickness:

0.062 inch ±0.007 inch•

Operating Temperature:

-40° to +85° C

Mating Cycles:

500 (minimum)

Insertion Force:

6 ounces per contact pair

Vibration:

10 Hz to 2 kHz at 15 Gs with 0.06-inch displacement

Contact Normal Force:

135 grams per contact

Connector Body:

Glass-filled polyphenylene sulfide, UL 94V-0

Insulation Resistance:

Greater than 50,000 Megaohms

Operating Humidity:

0 to 95% with no condensation

Connector Mating Surfaces
The design of the connector mating surface (or “gold fingers”) is the core of the STD 32 Bus Specification. This design not only allows the number of contacts to increase from 56 to 136 but also provides a backward-compatible platform for the thousands of existing STD I/O cards currently available for the STD Bus.

Mating Surface Specifications

PCB Thickness:

0.062 Inch ±0.007 inch

Plating:

30 µinches of gold over 50 µinches of nickel

Design:

Conforms to STD 32 P/E finger dimensions

Backplane
Another critical component in an STD 32 system is the backplane. The backplane design incorporates several important features including increased backplane signal impedance. A higher backplane signal impedance means “cleaner” signals are sent across the backplane. That is, ringing and reflections are minimized. This is especially important during signal transitions between the TTL threshold regions of 0.8V and 2.0V (see Figure 2).

Backplane Specifications

Minimum Center-to-Center Trace Spacing:

16 mil

Minimum Trace Width:

8 mil

Number of Copper Planes:

5 maximum

Unloaded Impedance:

55 ohms (minimum)

Copper Clad Thickness:

2 oz.

Backplane PCB Thickness:

0.093 inch (minimum)

Electrical

Pin Descriptions
See Figures 3 and 4.

Clock Frequency
The STD 32 Bus uses the signal CLOCK* for synchronous communication between Bus Masters (CPUs) and peripheral boards, and for other system management features such as arbitration. The Permanent Master is responsible for driving CLOCK* in all systems. The CLOCK* frequency is 8 MHz.

Transfer Types
STD 32 defines five classes of backplane transfers for communication between Bus Masters and peripherals. Standard Architecture (SA) transfers define compatible cycles for older STD 80 Series peripherals. Both 8- and 16-bit SA transfers are allowed through dynamic bus sizing. Extended Architecture (EA) transfers support 8-, 16-, and 32-bit data widths with a transfer cycle as short as one CLOCK* cycle. The maximum bandwidth for EA transfers is 32 Mbytes/second (see Figure 5). The cycle performed is dynamically sensed by the Bus Master from control signals that the peripheral returns. The default cycle is an SA 8-bit (SA8) cycle to remain compatible with older technology cards designed around the STD 80 Series specification.

Address Space
STD 32 supports a full 32-bit address space for memory cycles and a full 16-bit address space for I/O cycles. Older boards that do not decode the full I/O address range are allowed if they decode the IOEXP signal. IOEXP is driven low by STD 32 CPU boards in the I/O range FC00h to FFFFh, and high for all other addresses.

This mechanism prevents I/O boards that decode less than 16 bits and IOEXP low from being redundantly mapped throughout the I/O space. All STD 32 I/O boards must decode the full 16-bit address space. STD 32 memory boards must decode 24 bits of address for SA cycles and 32 bits of address for EA cycles.

Standard Architecture (SA) Cycles
SA cycles are nominally five CLOCK* cycles. The upper 8 bits of memory address (A16 to A23) is multiplexed with the data lines to allow the full, 16 Mbyte address range required by 286 and 386SX processors. This multiplexing scheme is compatible with STD 80 Series boards. 8-bit data transfers are performed unless the memory board being accessed returns MEM16* at the beginning of the cycle. When MEM16* is returned, a 16-bit SA cycle is defined (SA16), and the additional data signals D8 to D15 are driven on non-multiplexed pins. I/O cycles can also be 16 bits if the signal IO16* is driven by the I/O board during the transfer.

Extended Architecture (EA) Cycles
STD 32’s default transfer is an SA class cycle. If, during the beginning of a cycle, EX8*, EX16*, or EX32* is driven low by a peripheral board, then Extended Architecture cycles are performed. EX8*, EX16*, and EX32* define 8-, 16-, and 32-bit EA CLOCK* cycle. EA cycles use separate data and address signals (not multiplexed) to allow pipelined execution of the transfer.

Direct Memory Access (DMA)
Backplane Direct Memory Access (DMA) transfers are also defined for the Extended Architecture, at up to 32 Mbytes/second. Each of the first 15 slots in an STD 32 card cage has a dedicated set of DMA control signals to allow for true backplane DMA transfers. Older technology DMA mechanisms on the STD bus have required front plane cabling.

Interrupt Topology
STD 32 defines five bussed interrupt signals and one slot-specific interrupt for application use and system management.

Bussed Interrupts
INTRQ*, INTRQ1*, INTRQ2*, INTRQ3*, and NMIRQ* are bussed signals between all STD 32 connectors, including Slot X. Bus Masters use these signals for interrupt signaling between peripherals or Bus Masters and other Bus Masters.

Slot-Specific Interrupts
Each of the first 15 slots of the STD 32 card cage has a dedicated interrupt between it and the Slot X connector (the last connector on the left side of the backplane). For Bus Masters that can interface to Slot X, this allows up to 15 interrupt sources in addition to the five bussed interrupts.

Multiprocessor Arbitration
The Slot X connector on STD 32 backplanes allows for a centralized arbitration scheme for up to 15 Bus Masters. Each slot has dedicated arbitration signals (MREQx*/MAKx*) which are used to gain control of the bus. EA Temporary Masters use the MREQx*/MAKx* signals for bus arbitration. SA Temporary Masters use a similar approach, but use the DREQx*/DAKx* signals for bus ownership. A centralized arbiter manages bus ownership between Temporary Masters and the Permanent Master. Rotating priority or optional fixed priority can be selected.

Compliance Levels
Compliance levels specify the capabilities of STD 32 board designs. Each bus-related feature, such as the ability to support EA or SA transfers, is given a mnemonic description to be used on data sheets and board specifications to assist customers in system configuration.

Board MODES
There are five board MODES within STD 32 as defined in Figure 6. MODES define how a board may be used. For instance, a CPU board would normally be a Permanent Master but when another Bus Master has control it might also support memory cycles to or from it by the Temporary Master. In this case the board would have two board MODES, Permanent Master and Memory Slave.

Compliance CLASSES
For each board MODE, there are several CLASSES of transfers supported for that CLASS. Standard Extended Architecture (EA) 8-, 16-, and 32-bit transfer CLASSES are defined as EA8, EA16, and EA32, respectively.

Compliance Product Description

Features (Requirements/Options)
Listed after the CLASS support for each board MODE is a string of features that are requirements and/or options that the board supports. Requirements are items such as interrupt support or DMA that a board needs in order to operate. Options are items that may be used by a board but are not required for operation. Possible features for STD 32 compliance codes are found in Figure 7.

Compliance Style
Technical data sheets for STD 32-compatible boards include a product descriptor. This shows that the board complies with the STD 32 specification in all board MODES, transfer CLASSES, and required or optional features listed (see Figure 8 below).

Figure 8. STD 32 Compliance

For example, a board that can be either a Permanent Master or a Temporary Master with full EA8, EA16, EA32, SA8, and SA16 transfer CLASS support, interrupt support, cascade interrupt control, and that supports SA8 memory transfers to or from it when it is not in control would have the following product descriptor:

STD 32 Compliance

Permanent Master:

EA32, EA16, EA8, SA16, SA8 - MX, MB, ICA, I

Temporary Master:

EA32, EA16, EA8, SA16, SA8 - {MX}, MB, ICA, I

Memory Slave:

SA8

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